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STM32F100X4 STM32F100x6 STM32F100x8 STM32F100xB
Low & medium-density value line, advanced ARM-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces
Features
Core: ARM 32-bit CortexTM-M3 CPU - 24 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance - Single-cycle multiplication and hardware division Memories - 16 to 128 Kbytes of Flash memory - 4 to 8 Kbytes of SRAM Clock, reset and supply management - 2.0 to 3.6 V application supply and I/Os - POR, PDR and programmable voltage detector (PVD) - 4-to-24 MHz crystal oscillator - Internal 8 MHz factory-trimmed RC - Internal 40 kHz RC - PLL for CPU clock - 32 kHz oscillator for RTC with calibration Low power - Sleep, Stop and Standby modes - VBAT supply for RTC and backup registers Debug mode - Serial wire debug (SWD) and JTAG interfaces DMA - 7-channel DMA controller - Peripherals supported: timers, ADC, SPIs, I2Cs, USARTs and DACs 1 x 12-bit, 1.2 s A/D converter (up to 16 channels) - Conversion range: 0 to 3.6 V - Temperature sensor 2 x 12-bit D/A converters Up to 80 fast I/O ports - 37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant
FBGA
LQFP100 14 x 14 mm LQFP64 10 x 10 mm LQFP48 7 x 7 mm
TFBGA64 (5 x 5 mm)
Up to 12 timers - Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter - 16-bit, 6-channel advanced-control timer: up to 6 channels for PWM output, dead time generation and emergency stop - One 16-bit timer, with 2 IC/OC, 1 OCN/PWM, dead-time generation and emergency stop - Two 16-bit timers, each with IC/OC/OCN/PWM, dead-time generation and emergency stop - 2 watchdog timers (Independent and Window) - SysTick timer: 24-bit downcounter - Two 16-bit basic timers to drive the DAC Up to 8 communications interfaces - Up to two I2C interfaces (SMBus/PMBus) - Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - Up to 2 SPIs (12 Mbit/s) - Consumer electronics control (CEC) interface CRC calculation unit, 96-bit unique ID ECOPACK(R) packages Device summary
Part number STM32F100C4, STM32F100R4 STM32F100C6, STM32F100R6 STM32F100C8, STM32F100R8, STM32F100V8 STM32F100CB, STM32F100RB, STM32F100VB

Table 1.
STM32F100X4 STM32F100x6 STM32F100x8 STM32F100xB
Reference

July 2010
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Contents
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 ARM(R) CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . . 14
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 14 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 15 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . . 17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.16.1 2.16.2 2.16.3 2.16.4 2.16.5 2.16.6
Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16 & TIM17) . 18 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.17 2.18 2.19 2.20 2.21
I C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Universal synchronous/asynchronous receiver transmitter (USART) . . . 20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 HDMI (high-definition multimedia interface) consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 21
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2.22 2.23 2.24 2.25 2.26
Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 4 5
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 5.3.14 5.3.15 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 35 Embedded reset and power control block characteristics . . . . . . . . . . . 35 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 54 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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Contents 5.3.16 5.3.17 5.3.18
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.1 6.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 81
7 8
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F100xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F100xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 36 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32F100xxB maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 40 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 44 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 HSE 4-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53.
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 LQPF100 - 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 75 LQFP64 - 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 76 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 77 LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 79 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. 40 Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. STM32F100xx value line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STM32F100xx value line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F100xx value line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM32F100xx value line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM32F100xx value line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Maximum current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 39 Maximum current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 39 Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 70 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 70 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 75 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 LQFP64 - 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 76 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 77 Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 78
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List of figures Figure 43. Figure 44. Figure 45.
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of the STM32F100X4, STM32F100x6, STM32F100x8 and STM32F100xB value line microcontrollers. In the rest of the document, the STM32F100X4 and STM32F100x6 are referred to as low-density devices while the STM32F100x8 and STM32F100xB are identified as medium-density devices. The STM32F100xx datasheet should be read in conjunction with the low- and mediumdensity STM32F100xx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F100xx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
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Description
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
2
Description
The STM32F100xx value line family incorporates the high-performance ARM CortexTM-M3 32-bit RISC core operating at a 24 MHz frequency, high-speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 8 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (up to two I2Cs, two SPIs, one HDMI CEC, and up to three USARTs), one 12-bit ADC, two 12-bit DACs, up to six general-purpose 16-bit timers and an advanced-control PWM timer. The STM32F100xx low- and medium-density value line family operates in the -40 to +85 C and -40 to +105 C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F100xx value line family includes devices in three different packages ranging from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included. These features make the STM32F100xx value line microcontroller family suitable for a wide range of applications such as application control and user interfaces, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Description
2.1
Device overview
The description below gives an overview of the complete range of peripherals proposed in this family. Figure 1 shows the general block diagram of the device family.
Table 2.
STM32F100xx features and peripheral counts Peripheral
STM32F100Cx 16 4 Advanced-control General-purpose SPI
2C
STM32F100Rx 128 8 16 4 1 5(1) 1(2) 1(3) 2(4) 1 1 16 channels 51 2 2 24 MHz 2.0 to 3.6 V 32 4 64 8 1 6 2 2 3 128 8
STM32F100Vx 64 8 1 6 2 2 3 1 16 channels 80 128 8
Flash - Kbytes SRAM - Kbytes Timers
32 4 1 5(1) 1(2) 1(3) 2(4)
64 8 1 6 2 2 3
Communication I interfaces USART CEC 12-bit synchronized ADC number of channels GPIOs 12-bit DAC Number of channels CPU frequency Operating voltage Operating temperatures Packages
1. TIM4 not present. 2. SPI2 is not present. 3. I2C2 is not present. 4. USART3 is not present.
1 10 channels 37
Ambient operating temperature: -40 to +85 C /-40 to +105 C (see Table 8) Junction temperature: -40 to +125 C (see Table 8) LQFP48 LQFP64, TFBGA64 LQFP100
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Description Figure 1.
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB STM32F100xx value line block diagram
1. Peripherals not present in low-density value line devices. 2. AF = alternate function on I/O port pin. 3. TA = -40 C to +85 C (junction temperature up to 105 C) or TA = -40 C to +105 C (junction temperature up to 125 C).
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Figure 2. Clock tree
Description
4. To have an ADC conversion time of 1.2 s, APB2 must be at 24 MHz.
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Description
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
2.2
2.2.1
Overview
ARM(R) CortexTM-M3 core with embedded Flash and SRAM
The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F100xx value line family having an embedded ARM core, is therefore compatible with all ARM tools and software.
2.3
Embedded Flash memory
Up to 128 Kbytes of embedded Flash memory is available for storing programs and data.
2.4
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
2.5
Embedded SRAM
Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Description
2.6
Nested vectored interrupt controller (NVIC)
The STM32F100xx value line embeds a nested vectored interrupt controller able to handle up to 41 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels.

Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt latency.
2.7
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 18 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines.
2.8
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 24 MHz.
2.9
Boot modes
At startup, boot pins are used to select one of three boot options:

Boot from user Flash Boot from system memory Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606.
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Description
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
2.10
Power supply schemes

VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
2.11
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
2.12
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.

MR is used in the nominal regulation mode (Run) LPR is used in the Stop mode Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.
2.13
Low-power modes
The STM32F100xx value line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Description
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.
Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.
2.14
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, DAC, I2C, USART, all timers and ADC.
2.15
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.16
Timers and watchdogs
The STM32F100xx devices include an advanced-control timer, six general-purpose timers, two basic timers and two watchdog timers. Table 3 compares the features of the advanced-control, general-purpose and basic timers.
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Description Table 3.
Timer
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Timer feature comparison
Counter resolution 16-bit Counter type Up, down, up/down Up, down, up/down Up Prescaler factor Any integer between 1 and 65536 Any integer between 1 and 65536 Any integer between 1 and 65536 Any integer between 1 and 65536 Any integer between 1 and 65536 DMA request Capture/compare Complementary generation channels outputs Yes 4 Yes
TIM1 TIM2, TIM3, TIM4 TIM15
16-bit
Yes
4
No
16-bit
Yes
2
Yes
TIM16, TIM17 TIM6, TIM7
16-bit
Up
Yes
1
Yes
16-bit
Up
Yes
0
No
2.16.1
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:

Input capture Output compare PWM generation (edge or center-aligned modes) One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.
2.16.2
General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16 & TIM17)
There are six synchronizable general-purpose timers embedded in the STM32F100xx devices (see Table 3 for differences). Each general-purpose timers can be used to generate PWM outputs, or as simple time base.
TIM2, TIM3, TIM4
STM32F100xx devices feature three synchronizable 4-channels general-purpose timers. These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or one-
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Description
pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining. TIM2, TIM3, TIM4 all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Their counters can be frozen in debug mode.
TIM15, TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output. The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with TIM1 via the Timer Link feature for synchronization or event chaining. TIM15 can be synchronized with TIM16 and TIM17. TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and independent DMA request generation Their counters can be frozen in debug mode.
2.16.3
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.
2.16.4
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
2.16.5
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
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Description
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
2.16.6
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It features:

A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source
2.17
IC bus
The IC bus interface can operate in multimaster and slave modes. It can support standard and fast modes. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.
2.18
Universal synchronous/asynchronous receiver transmitter (USART)
The STM32F100xx value line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3). The available USART interfaces communicate at up to 3 Mbit/s. They provide hardware management of the CTS and RTS signals, they support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller.
2.19
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 12 Mbit/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. Both SPIs can be served by the DMA controller.
2.20
HDMI (high-definition multimedia interface) consumer electronics control (CEC)
The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Description
2.21
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.
2.22
Remap capability
This feature allows the use of a maximum number of peripherals in a given application. Indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable. This has the advantage of making board design and port usage much more flexible. For details refer to Table 4: STM32F100xx pin definitions; it shows the list of remappable alternate functions and the pins onto which they can be remapped. See the STM32F10xxx reference manual for software considerations.
2.23
ADC (analog-to-digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
2.24
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in noninverting configuration. This dual digital Interface supports the following features:

two DAC converters: one for each output channel up to 10-bit output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channels' independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+
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Description
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Eight DAC trigger inputs are used in the STM32F100xx. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.
2.25
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.
2.26
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Pinouts and pin description
3
Pinouts and pin description
Figure 3. STM32F100xx value line LQFP100 pinout
VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LQFP100
VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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Pinouts and pin description Figure 4.
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
STM32F100xx value line LQFP64 pinout
VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
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Figure 5.
STM32F100xx value line LQFP48 pinout
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2
48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12
PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Figure 6. STM32F100xx value line TFBGA64 ballout
1 2 3 4 5 6
Pinouts and pin description
7
8
A
PC14PC13OSC32_IN TAMPER-RTC
PB9
PB4
PB3
PA15
PA14
PA13
B
PC15OSC32_OUT
VBAT
PB8
BOOT0
PD2
PC11
PC10
PA12
C
OSC_IN
VSS_4
PB7
PB5
PC12
PA10
PA9
PA11
D
OSC_OUT
VDD_4
PB6
VSS_3
VSS_2
VSS_1
PA8
PC9
E
NRST
PC1
PC0
VDD_3
VDD_2
VDD_1
PC7
PC8
F
VSSA
PC2
PA2
PA5
PB0
PC6
PB15
PB14
G
VREF+
PA0-WKUP
PA3
PA6
PB1
PB2
PB10
PB13
H
VDDA
PA1
PA4
PA7
PC4
PC5
PB11
PB12
AI15494
Table 4.
Pins TFBGA64
STM32F100xx pin definitions
I / O level(2) Alternate functions(3)(4) Main function(3) (after reset) PE2 PE3 PE4 PE5 PE6 VBAT PC13(6) TAMPER-RTC Type(1)
LQFP100
LQFP64
LQFP48
Pin name
Default
Remap
1 2 3 4 5 6 7
1 2
B2 A2
1 2
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPERRTC(5)
I/O FT I/O FT I/O FT I/O FT I/O FT S I/O
TRACECLK TRACED0 TRACED1 TRACED2 TRACED3
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Pinouts and pin description Table 4.
Pins Type(1) TFBGA64 LQFP100 LQFP64 LQFP48 Pin name
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
STM32F100xx pin definitions (continued)
I / O level(2) Alternate functions(3)(4) Main function(3) (after reset)
Default
Remap
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
3 4 5 6 7 8 9
A1 B1 C1 D1 E1 E3 E2
3 4 5 6 7 8 9
PC14OSC32_IN(5) PC15OSC32_OUT(5) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4
I/O I/O S S I O I/O I/O I/O I/O I/O S S S S I/O I/O I/O I/O S S I/O I/O I/O I/O I/O
PC14(6) PC15(6) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0 PA1 PA2 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4
OSC32_IN OSC32_OUT
ADC1_IN10 ADC1_IN11 ADC1_IN12 ADC1_IN13
10 F2 11 -(7) 12 F1 G1
13 H1
14 G2 10 15 H2 11 16 F3 12 17 G3 13 18 C2 19 D2 -
WKUP / USART2_CTS(12)/ ADC1_IN0 / TIM2_CH1_ETR(12) USART2_RTS(12)/ ADC1_IN1 / TIM2_CH2(12) USART2_TX(12)/ ADC1_IN2 / TIM2_CH3(12)/ TIM15_CH1(12) USART2_RX(12)/ ADC1_IN3 / TIM2_CH4(12) / TIM15_CH2(12)
20 H3 14 21 F4 15 22 G4 16 23 H4 17 24 H5 -
SPI1_NSS(12)/ADC1_IN4 USART2_CK(12) / DAC1_OUT SPI1_SCK(12)/ADC1_IN5 / DAC2_OUT SPI1_MISO(12)/ADC1_IN6 / TIM3_CH1(12) SPI1_MOSI(12)/ADC1_IN7 / TIM3_CH2(12) ADC1_IN14 TIM1_BKIN / TIM16_CH1 TIM1_CH1N / TIM17_CH1
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Table 4.
Pins Type(1) TFBGA64 LQFP100 LQFP64 LQFP48 Pin name
Pinouts and pin description
STM32F100xx pin definitions (continued)
I / O level(2) Alternate functions(3)(4) Main function(3) (after reset) PC5 PB0 PB1 PB2/BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 SPI2_NSS(9)/ I2C2_SMBA(8)/ TIM1_BKIN(12)/USART3_CK(12) SPI2_SCK(9) /TIM1_CH1N(12) USART3_CTS(12) SPI2_MISO(9)/ TIM1_CH2N(12) / USART3_RTS(12) SPI2_MOSI(9) / TIM1_CH3N / TIM15_CH1N(12) TIM15_CH1 TIM15_CH2 USART3_TX USART3_RX USART3_CK USART3_CTS TIM4_CH1(10) / USART3_RTS TIM4_CH2(10) TIM4_CH3(10) I2C2_SCL(8)/USART3_TX (12) I2C2_SDA(8)/USART3_RX(12) TIM1_ETR TIM1_CH1N TIM1_CH1 TIM1_CH2N TIM1_CH2 TIM1_CH3N TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM2_CH3 / CEC TIM2_CH4
Default
Remap
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
25 H6
-
PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14
I/O I/O I/O I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT
ADC1_IN15 ADC1_IN8/TIM3_CH3(12) ADC1_IN9/TIM3_CH4
(12)
26 F5 18 27 G5 19 28 G6 20 -
TIM1_CH2N TIM1_CH3N
29 G7 21 30 H7 22 31 D6 23 32 E6 24 33 H8 25 34 G8 26 35 F8 27 36 F7 28 -
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Pinouts and pin description Table 4.
Pins Type(1) TFBGA64 LQFP100 LQFP64 LQFP48 Pin name
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
STM32F100xx pin definitions (continued)
I / O level(2) Alternate functions(3)(4) Main function(3) (after reset) PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 JTMSSWDIO Not connected VSS_2 VDD_2 PA14 S S I/O FT VSS_2 VDD_2 JTCK/SWCL K JTDI PC10 PC11 PC12 OSC_IN
(11)
Default
Remap TIM4_CH4(10) TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
-
-
-
PD15 PC6 PC7 PC8
I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT
37 F6 38 E7 39 E8 40 D8
-
PC9 PA8 PA9 PA10 PA11 PA12 PA13
41 D7 29 42 C7 30 43 C6 31 44 C8 32 45 B8 33 46 A8 34 -
USART1_CK / MCO / TIM1_CH1 USART1_TX(12) / TIM1_CH2 USART1_RX
(12)
TIM15_BKIN TIM17_BKIN
/ TIM1_CH3
USART1_CTS / TIM1_CH4 USART1_RTS / TIM1_ETR PA13
47 D5 35 48 E5 36 49 A7 37
PA14 TIM2_CH1_ETR / PA15/ SPI1_NSS USART3_TX USART3_RX USART3_CK
77 78 79 80 81 82 83 84 85 86 87 88 89
50 A6 38 51 B7 52 B6 53 C5 5 6 C1 D1 5 6
PA15 PC10 PC11 PC12 PD0 PD1 PD2
I/O FT I/O FT I/O FT I/O FT I/O FT
I/O FT OSC_OUT(11) I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PD2 PD3 PD4 PD5 PD6 PD7 JTDO TIM3_ETR USART2_CTS USART2_RTS USART2_TX USART2_RX USART2_CK TIM2_CH2 / PB3 TRACESWO SPI1_SCK
54 B5 -
PD3 PD4 PD5 PD6 PD7 PB3
55 A5 39
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Table 4.
Pins Type(1) TFBGA64 LQFP100 LQFP64 LQFP48 Pin name
Pinouts and pin description
STM32F100xx pin definitions (continued)
I / O level(2) Alternate functions(3)(4) Main function(3) (after reset)
Default
Remap
90 91 92 93 94 95 96 97 98 99
56 A4 40 57 C4 41 58 D3 42 59 C3 43 60 B4 44 61 B3 45 62 A3 46 -
PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3
I/O FT I/O I/O FT I/O FT I I/O FT I/O FT I/O FT I/O FT S S
NJTRST PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 TIM4_CH3(10)(12) / TIM16_CH1(12) / CEC(12) TIM4_CH4(10)(12) / TIM17_CH1(12) TIM4_ETR(10) I2C1_SMBA / TIM16_BKIN I2C1_SCL(12)/ TIM4_CH1(10)(12) TIM16_CH1N I2C1_SDA(12)/ TIM17_CH1N TIM4_CH2(10)(12)
PB4 / TIM3_CH1 SPI1_MISO TIM3_CH2 / SPI1_MOSI USART1_TX USART1_RX
I2C1_SCL I2C1_SDA
63 D4 47
100 64 E4 48
1. I = input, O = output, S = supply, HiZ= high impedance. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead. 8. I2C2 is not present on low-density value line devices. 9. SPI2 is not present on low-density value line devices. 10. TIM4 is not present on low-density value line devices. 11. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. 12. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
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Memory mapping
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
4
Memory mapping
The memory map is shown in Figure 7. Figure 7. Memory map
APB memory space 0xFFFF FFFF 0x4002 3400 0x4002 3000 0x4002 2400 0xFFFF FFFF 0x4002 2000 0x4002 1400 0x4002 1000 7 0xE010 0000 0xE000 0000 Cortex-M3 internal peripherals 0x4002 0400 0x4002 0000 0x4001 4C00 0x4001 4800 6 0x4001 4400 0x4001 4000 0xC000 0000 0x4001 3C00 0x4001 3800 0x4001 3400 5 0xA000 0000 0x4001 3000 0x4001 2C00 0x4001 2800 0x4001 2400 4 0x1FFF FFFF 0x1FFF F80F 0x8000 0000 0x1FFF F800 3 0x1FFF F000 0x6000 0000 System memory Option Bytes 0x4001 1C00 0x4001 1800 rese rved 0x4001 1400 0x4001 1000 0x4001 0C00 0x4001 0800 0x4001 0400 0x4001 0000 0x4000 7C00 0x4000 7800 0x4000 7400 2 Peripherals reserved 0x4000 7000 0x4000 6C00 0x4000 5C00 0x4000 5800 1 SRAM 0x0801 FFFF 0x4000 5400 0x4000 4C00 0x2000 0000 0x4000 4800 0x4000 4400 0x4000 3C00 0 0x0800 0000 0x0000 0000 Aliased to Flash or system memory depending on 0x0000 0000 BOOT pins Flash memory 0x4000 3800 0x4000 3400 0x4000 3000 0x4000 2C00 0x4000 2800 0x4000 1800 0x4000 1400 0x4000 1000 0x4000 0C00 0x4000 0800 0x4000 0400 0x4000 0000 USART1 reserved SPI1 TIM1 reserved ADC1 reserved Port E Port D Port C Port B Port A EXTI AFIO reserved CEC DAC PWR BKP I2C2 reserved I2C1 reserved USART3 USART2 reserved SPI2 reserved IWDG WWDG RTC reserved TIM7 TIM6 reserved TIM4 TIM3 TIM2 ai17156 reserved CRC reserved Flash interface reserved RCC reserved DMA reserved TIM17 TIM16 TIM15 reserved
0x4000 0000
Reserved
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Electrical characteristics
5
5.1
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
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Electrical characteristics
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Figure 8.
Pin loading conditions
Figure 9.
Pin input voltage
STM32F10xxx pin C = 50 pF
VIN
STM32F10xxx pin
ai14123b
ai14124b
5.1.6
Power supply scheme
Figure 10. Power supply scheme
VBAT
1.8-3.6V
Po wer swi tch
Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers)
OUT
Level shifter
GP I/Os
IN
IO Logic Kernel logic (CPU, Digital & Memories)
VDD
VDD 1/2/3/4/5 VSS
Regulator
5 x 100 nF + 1 x 4.7 F
VDD VREF
1/2/3/4/5
VDDA VREF+ VREFVSSA
ai14125d
10 nF + 1 F
10 nF + 1 F
ADC
Analog: RCs, PLL, ...
Caution:
In Figure 10, the 4.7 F capacitor must be connected to VDD3.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Electrical characteristics
5.1.7
Current consumption measurement
Figure 11. Current consumption measurement scheme
IDD_VBAT VBAT
IDD VDD
VDDA
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5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics, Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5.
Symbol VDD VSS VIN |VDDx| |VSSX VSS|
Voltage characteristics
Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different VDD power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min -0.3 VSS 0.3 VSS 0.3 Max 4.0 +5.5 VDD+0.3 50 mV 50 see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) V Unit
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 6: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is induced by VINDoc ID 16455 Rev 5
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Electrical characteristics Table 6.
Symbol IVDD IVSS IIO
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Current characteristics
Ratings Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines (sink)
(1)
Max. 150 150 25 25 5 5 +5 / -0 5 25
Unit
Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin IINJ(PIN) (2)(3) Injected current on High-speed external OSC_IN and Lowspeed external OSC_IN pins Injected current on the PA5, PA6 and PA7 pins(4) Injected current on any other pin IINJ(PIN)(2)
(4)
mA
Total injected current (sum of all I/O and control pins)(4)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VINTable 7.
Thermal characteristics
Ratings Storage temperature range Maximum junction temperature Value -65 to +150 150 Unit C C
Symbol TSTG TJ
5.3
5.3.1
Operating conditions
General operating conditions
Table 8.
Symbol fHCLK fPCLK1 fPCLK2 VDD
General operating conditions
Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Conditions Min 0 0 0 2 2 Must be the same potential as VDD 2.4 Max 24 24 24 3.6 3.6 V 3.6 V MHz Unit
VDDA(1)
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Table 8.
Symbol VBAT
Electrical characteristics
General operating conditions (continued)
Parameter Backup operating voltage LQFP100 Conditions Min 1.8 Max 3.6 434 444 mW TFBGA64 LQFP48 Ambient temperature for 6 suffix version Maximum power dissipation Low power dissipation
(3)
Unit V
PD
Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(2)
LQFP64
308 363 -40 -40 -40 -40 -40 -40 85 C 105 105 C 125 105 C 125
TA Ambient temperature for 7 suffix version TJ Junction temperature range 7 suffix version
1. When the ADC is used, refer to Table 41: ADC characteristics. 2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 80). 3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 80).
Maximum power dissipation Low power dissipation 6 suffix version
(3)
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for TA. Table 9.
Symbol tVDD
Operating conditions at power-up / power-down
Parameter VDD rise time rate VDD fall time rate Min 0 20 Max Unit s/V

5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 10 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8.
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Electrical characteristics Table 10.
Symbol
.
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Embedded reset and power control block characteristics
Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Min 2.1 2 2.19 2.09 2.28 2.18 2.38 2.28 2.47 2.37 2.57 2.47 2.66 2.56 2.76 2.66 Typ 2.18 2.08 2.28 2.18 2.38 2.28 2.48 2.38 2.58 2.48 2.68 2.58 2.78 2.68 2.88 2.78 100 Falling edge Rising edge 1.8(1) 1.84 1.88 1.92 40 1.5 2.5 4.5 1.96 2.0 Max 2.26 2.16 2.37 2.27 2.48 2.38 2.58 2.48 2.69 2.59 2.79 2.69 2.9 2.8 3 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV ms
VPVD
Programmable voltage detector level selection
PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge)
VPVDhyst
(2)
PVD hysteresis Power on/power down reset threshold PDR hysteresis
VPOR/PDR VPDRhyst
(2)
tRSTTEMPO(2) Reset temporization
2. Guaranteed by design, not tested in production.
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Electrical characteristics
5.3.4
Embedded reference voltage
The parameters given in Table 11 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 11.
Symbol VREFINT
Embedded internal reference voltage
Parameter Internal reference voltage Conditions -40 C < TA < +105 C -40 C < TA < +85 C Min 1.16 1.16 Typ 1.20 1.20 5.1 Max 1.26 1.24 17.1(2) Unit V V s
ADC sampling time when TS_vrefint(1) reading the internal reference voltage Internal reference voltage VRERINT(2) spread over the temperature range TCoeff(2) Temperature coefficient VDD = 3 V 10 mV
10 100
mV ppm/C
1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 11: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:

All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 12 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8.
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Electrical characteristics Table 12.
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Maximum current consumption in Run mode, code with data processing running from Flash
Max(1) Parameter Conditions fHCLK TA = 85 C 24 MHz External clock (2), all peripherals enabled 16 MHz 8 MHz 24 MHz External clock(2), all peripherals disabled 16 MHz 8 MHz 15.4 11 6.7 10.3 7.8 5.1 TA = 105 C 15.7 11.5 6.9 mA 10.5 8.1 5.3 Unit
Symbol
IDD
Supply current in Run mode
1. Based on characterization, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 13.
Maximum current consumption in Run mode, code with data processing running from RAM
Max(1) Parameter Conditions fHCLK TA = 85 C 24 MHz External clock (2), all peripherals enabled 16 MHz 8 MHz 24MHz External clock(2) all peripherals disabled 16 MHz 8 MHz 14.5 10 6 9.3 6.8 4.4 TA = 105 C 15 10.5 6.3 mA 9.7 7.2 4.7 Unit
Symbol
IDD
Supply current in Run mode
1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Electrical characteristics
Figure 12. Maximum current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled
Figure 13. Maximum current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled
Table 14.
STM32F100xxB maximum current consumption in Sleep mode, code running from Flash or RAM
Max(1) Parameter Conditions fHCLK TA = 85 C 24 MHz External clock(2) all peripherals enabled 16 MHz 8 MHz 24 MHz External clock(2), all peripherals disabled 16 MHz 8 MHz 9.6 7.1 4.5 3.8 3.3 2.7 TA = 105 C 10 7.5 4.8 mA 4 3.5 3 Unit
Symbol
IDD
Supply current in Sleep mode
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics Table 15.
Symbol
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Typical and maximum current consumptions in Stop and Standby modes
Typ(1) Parameter Conditions Max Unit
VDD/VBAT VDD/ VBAT VDD/VBAT TA = TA = = 2.0 V = 2.4 V = 3.3 V 85 C 105 C
Regulator in Run mode, Low-speed and high-speed internal RC oscillators and highspeed oscillator OFF (no Supply current independent watchdog) in Stop mode Regulator in Low-Power mode, Low-speed and high-speed internal RC oscillators and highspeed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Low-speed internal RC oscillator Supply current ON, independent watchdog OFF in Standby mode Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF Backup Low-speed oscillator and RTC IDD_VBAT domain supply ON current
1. Typical values are measured at TA = 25 C.
23.5
24
190
350
13.5
14
170
330
IDD
2.6 2.4
3.4 3.2
-
-
A
1.7
2
4
5
0.9
1.1
1.4
1.9
2.2
Figure 14. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values
2.00 1.50
IDD_VBAT (A)
3.6 V
1.00 0.50 0.00 -45C 25C 85C 105C
Temperature (C)
3.3 V 2.4 V 2V
ai15792
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Electrical characteristics
Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V
Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V
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Electrical characteristics
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Figure 17. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V
Typical current consumption
The MCU is placed under the following conditions:

All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4
The parameters given in Table 16 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Table 16.
Electrical characteristics
Typical current consumption in Run mode, code with data processing running from Flash
Typical values(1) Conditions fHCLK Unit
Symbol Parameter
All peripherals All peripherals enabled(2) disabled 12.8 9.3 5.1 3.2 2.1 1.55 1.3 1.1 12.2 8.5 4.6 2.6 1.5 0.9 0.65 0.45 9.3 6.6 3.9 2.5 1.75 1.4 1.2 1.05
24 MHz 16 MHz 8 MHz Running on high-speed external clock with an 8 MHz crystal(3) 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Run mode 125 kHz 24 MHz 16 MHz 8 MHz Running on high-speed internal RC (HSI) 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz
1. Typical values are measures at TA = 25 C, VDD = 3.3 V.
mA 8.6 6 3.3 1.9 1.15 0.8 0.6 0.43
2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency when fHCLK < 8 MHz, the PLL is used when fHCLK > 8 MHz.
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Electrical characteristics Table 17.
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Typical current consumption in Sleep mode, code running from Flash or RAM
Typical values(1) Conditions fHCLK Unit
Symbol Parameter
All peripherals All peripherals enabled(2) disabled 7.3 5.2 2.8 2 1.5 1.25 1.1 1.05 6.65 4.5 2.2 1.35 0.85 0.6 0.5 0.4 2.6 2 1.3 1.1 1.1 1 1 0.95
24 MHz 16 MHz 8 MHz Running on high-speed external clock with an 8 MHz crystal(3) 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Sleep mode 125 kHz 24 MHz 16 MHz 8 MHz Running on high-speed internal RC (HSI) 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz
1. Typical values are measures at TA = 25 C, VDD = 3.3 V.
mA 1.9 1.4 0.7 0.55 0.45 0.41 0.39 0.37
2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency when fHCLK > 8 MHz, the PLL is used when fHCLK > 8 MHz.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed under the following conditions:

all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption - - with all peripherals clocked off with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in Table 5.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Table 18. Peripheral current consumption
Peripheral TIM2 TIM3 TIM4 TIM6 TIM7 DAC APB1 WWDG SPI2 USART2 USART3 I2C1 I2C2 HDMI CEC GPIO A GPIO B GPIO C GPIO D GPIO E ADC1 APB2 SPI1 USART1 TIM1 TIM15 TIM16 TIM17 0.12 0.27 0.63 0.33 0.26 0.25
(3)
Electrical characteristics
Typical consumption at 25 C(1) 0.52 0.46 0.5 0.125 0.19 0.5(2) 0.13 0.2 0.38 0.32 0.27 0.28 0.16 0.25 0.12 0.18 0.15 0.15 1.15
Unit
mA
1. fHCLK = fAPB1 = fAPB2 = 24 MHz, default prescaler value for each peripheral. 2. Specific conditions for DAC: EN1 bit in DAC_CR register set to 1. 3. Specific conditions for ADC: fHCLK = 24 MHz, fAPB1 = fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit in the ADC_CR2 register is set to 1.
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 19 result from tests performed using an high-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in Table 8.
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Electrical characteristics Table 19.
Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) Cin(HSE)
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
High-speed external user clock characteristics
Parameter User external clock source frequency(1) OSC_IN input pin high level voltage(1) OSC_IN input pin low level voltage(1) OSC_IN high or low time(1) OSC_IN rise or fall time(1) OSC_IN input capacitance(1) cycle(1) VSS VIN VDD 45 5 55 1 Conditions Min 1 0.7VDD VSS 16 ns 20 pF % A Typ 8 Max 24 VDD V 0.3VDD Unit MHz
DuCy(HSE) Duty IL
OSC_IN Input leakage current
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an low-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in Table 8. Table 20.
Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) Cin(LSE)
Low-speed external user clock characteristics
Parameter User external clock source frequency(1) OSC32_IN input pin high level voltage(1) OSC32_IN input pin low level voltage(1) OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) 5 30 VSS VIN VDD 70 1 0.7VDD VSS 450 ns 50 pF % A Conditions Min Typ 32.768 Max 1000 VDD V 0.3VDD Unit kHz
OSC32_IN input capacitance(1) cycle(1)
DuCy(LSE) Duty IL
OSC32_IN Input leakage current
1. Guaranteed by design, not tested in production.
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Electrical characteristics
Figure 18. High-speed external clock source AC timing diagram
VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t
External clock source
fHSE_ext OSC _IN
IL STM32F10xxx ai14127b
Figure 19. Low-speed external clock source AC timing diagram
VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t
External clock source
fLSE_ext
OSC32_IN
IL STM32F10xxx ai14140c
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 21. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
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Electrical characteristics Table 21.
Symbol fOSC_IN RF CL1 CL2(3) i2 gm tSU(HSE)
(5)
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
HSE 4-24 MHz oscillator characteristics(1)(2)
Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(4) HSE driving current Oscillator transconductance Startup time RS = 30 VDD = 3.3 V VIN = VSS with 30 pF load Startup VDD is stabilized 25 2 Conditions Min 4 Typ 8 200 30 Max 24 Unit MHz k pF
1
mA mA/V ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. It is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. 4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Figure 20. Typical application with an 8 MHz crystal
Resonator with integrated capacitors CL1 OSC_IN 8 MH z resonator CL2 REXT(1) OSC_OU T RF Bias controlled gain STM32F10xxx ai14128b fHSE
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Note:
Electrical characteristics
For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Table 22.
Symbol RF CL1 CL2(2) I2 gm tSU(LSE)
(4)
Caution:
LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) LSE driving current Oscillator transconductance Startup time VDD is stabilized RS = 30 K VDD = 3.3 V VIN = VSS 5 3 Conditions Min Typ 5 15 Max Unit M pF
1.4
A A/V s
1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs above the table. 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Figure 21. Typical application with a 32.768 kHz crystal
Resonator with integrated capacitors CL1 OSC32_IN 32.768 KH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F10xxx fLSE
ai14129b
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Electrical characteristics
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
5.3.7
Internal clock source characteristics
The parameters given in Table 23 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8.
High-speed internal (HSI) RC oscillator
Table 23.
Symbol fHSI Frequency TA = -40 to 105 C ACCHSI Accuracy of HSI oscillator(2) TA = -10 to 85 C TA = 0 to 70 C TA = 25 C tsu(HSI) IDD(HSI) HSI oscillator startup time HSI oscillator power consumption -2.7 -2 -2 -0.7 1 80
HSI oscillator characteristics(1)
Parameter Conditions Min Typ 8 3 2.5 2.5 1 2 100 Max Unit MHz % % % % s A
1. VDD = 3.3 V, TA = -40 to 105 C C unless otherwise specified. 2. Based on characterization, not tested in production.
Low-speed internal (LSI) RC oscillator
Table 24.
Symbol fLSI fLSI(T) tsu(LSI)
(3)
LSI oscillator characteristics (1)
Parameter Frequency Temperature-related frequency LSI oscillator startup time LSI oscillator power consumption 0.65 drift(2) Min 30 -9 Typ 40 Max 60 9 85 1.2 Unit kHz % s A
IDD(LSI)(3)
1. VDD = 3 V, TA = -40 to 105 C C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 25 are measured on a wakeup phase with an 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:

Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Table 25.
Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1)
Electrical characteristics
Low-power mode wakeup timings
Parameter Wakeup from Sleep mode Wakeup from Stop mode (regulator in run mode) Wakeup from Stop mode (regulator in low-power mode) Wakeup from Standby mode Typ 1.8 3.6 s 5.4 50 s Unit s
1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 26 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 26.
Symbol
PLL characteristics
Value Parameter PLL input clock(2) Min(1) 1 40 16 Typ 8.0 Max(1) 24 60 24 200 300 Unit MHz % MHz s ps
fPLL_IN fPLL_OUT tLOCK Jitter
PLL input clock duty cycle PLL multiplier output clock PLL lock time Cycle-to-cycle jitter
1. Based on device characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT.
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Electrical characteristics
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = -40 to 105 C unless otherwise specified. Table 27.
Symbol tprog tERASE tME
Flash memory characteristics
Parameter 16-bit programming time Page (1 KB) erase time Mass erase time Conditions TA-40 to +105 C TA -40 to +105 C TA -40 to +105 C Read mode fHCLK = 24 MHz, VDD = 3.3 V Min(1) 40 20 20 Typ 52.5 Max(1) 70 40 40 20 5 50 2 3.6 Unit s ms ms mA mA A V
IDD
Supply current
Write / Erase modes fHCLK = 24 MHz, VDD = 3.3 V Power-down mode / Halt, VDD = 3.0 to 3.6 V
Vprog
Programming voltage
1. Guaranteed by design, not tested in production.
Table 28.
Symbol NEND
Flash memory endurance and data retention
Value Parameter Endurance Conditions TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 1 kcycle(2) at TA = 85 C kcycle(2) at TA = 105 C Min(1) 10 30 10 20 Years Unit Typ Max kcycles
tRET
Data retention 1
10 kcycles(2) at TA = 55 C
1. Based on characterization not tested in production. 2. Cycling performed over the whole temperature range.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Electrical characteristics
5.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in Table 29. They are based on the EMS levels and classes defined in application note AN1709. Table 29.
Symbol
EMS characteristics
Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Conditions VDD 3.3 V, TA +25 C, fHCLK 24 MHz, LQFP100 package, conforms to IEC 61000-4-2 Level/Class
VFESD
2B
VEFTB
VDD3.3 V, TA +25 C, Fast transient voltage burst limits to be fHCLK 24 MHz, LQFP100 applied through 100 pF on VDD and VSS pins package, conforms to to induce a functional disturbance IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:

Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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Electrical characteristics
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 30. EMI characteristics
Conditions Monitored frequency band 0.1 MHz to 30 MHz 30 MHz to 130 MHz 130 MHz to 1GHz SAE EMI Level Max vs. [fHSE/fHCLK] Unit 8/24 MHz 9 16 19 4 dBV
Symbol Parameter
SEMI
Peak level
VDD 3.6 V, TA 25C, LQFP100 package compliant with SAE J1752/3
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 31.
Symbol VESD(HBM) VESD(CDM)
ESD absolute maximum ratings
Ratings Electrostatic discharge voltage (human body model) Conditions TA +25 C conforming to JESD22-A114 Class 2 II Maximum Unit value(1) 2000 V 500
Electrostatic discharge TA +25 C voltage (charge device model) conforming to JESD22-C101
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up performance:

A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD78 IC latch-up standard. Table 32.
Symbol LU
Electrical sensitivities
Parameter Static latch-up class Conditions TA +105 C conforming to JESD78 Class II level A
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Electrical characteristics
5.3.12
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 33 are derived from tests performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL compliant.
Table 33.
Symbol
I/O static characteristics
Parameter Conditions Min -0.5 -0.5 0.41 (VDD-2) +1.3 0.42 (VDD-2) +1 200 5% VDD(3) VSS VIN VDD Standard I/Os VIN = 5 V I/O FT 1 A 3 30 30 40 40 5 50 50 k k pF Typ Max 0.28 (VDD-2) +0.8 0.32 (VDD-2) +0.75 V VDD+0.5 5.5 mV mV Unit
Standard I/O input low level voltage VIL I/O FT(1) input low level voltage Standard I/O input high level voltage VIH I/O FT(1) input high level voltage Standard I/O Schmitt trigger voltage hysteresis(2) Vhys I/O FT Schmitt trigger voltage hysteresis(2)
Ilkg
Input leakage current(4)
RPU RPD CIO
Weak pull-up equivalent resistor(5) Weak pull-down equivalent resistor(5) I/O pin capacitance
VIN VSS VIN VDD
1. FT = 5V tolerant. To sustain a voltage higher than VDD+0.5 the internal pull-up/pull-down resistors must be disabled. 2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by design, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 22 and Figure 23 for standard I/Os, and in Figure 24 and Figure 25 for 5 V tolerant I/Os.
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Figure 22. Standard I/O input characteristics - CMOS port
Figure 23. Standard I/O input characteristics - TTL port
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Figure 24. 5 V tolerant I/O input characteristics - CMOS port
Electrical characteristics
Figure 25. 5 V tolerant I/O input characteristics - TTL port
Output driving current
The GPIOs (general-purpose inputs/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 6). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 6).
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Output voltage levels
Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. Table 34.
Symbol VOL(1) VOH
(2)
Output voltage characteristics
Parameter Output Low level voltage for an I/O pin when 8 pins are sunk at the same time Output High level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Conditions TTL port, IIO = +8 mA, 2.7 V < VDD < 3.6 V CMOS port IIO = +8 mA 2.7 V < VDD < 3.6 V Min Max 0.4 V VDD-0.4 0.4 V 2.4 1.3 V VDD-1.3 0.4 V VDD-0.4 Unit
VOL(1) VOH
(2)
VOL(1) VOH
(2)
IIO = +20 mA(3) 2.7 V < VDD < 3.6 V
VOL(1) VOH
(2)
IIO = +6 mA(3) 2 V < VDD < 2.7 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production.
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Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 26 and Table 35, respectively. Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 35.
MODEx [1:0] bit value(1)
I/O AC characteristics(1)
Symbol Parameter Conditions CL = 50 pF, VDD = 2 V to 3.6 V Max 2(3) 125(3) CL = 50 pF, VDD = 2 V to 3.6 V 125 CL= 50 pF, VDD = 2 V to 3.6 V
(3)
Unit MHz
fmax(IO)out Maximum frequency(2) 10 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time
ns
fmax(IO)out Maximum frequency(2) 01 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time
10(3) 25(3)
MHz
CL= 50 pF, VDD = 2 V to 3.6 V 25(3) CL = 50 pF, VDD = 2 V to 3.6 V CL = 30 pF, VDD = 2.7 V to 3.6 V 24 5(3) 8(3) 12(3) 5(3) 8(3) 12(3) 10(3)
ns
fmax(IO)out Maximum frequency(2) Output high to low level fall time
MHz
tf(IO)out 11
CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V
ns
tr(IO)out
Output low to high level rise time Pulse width of external signals detected by the EXTI controller
CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V
-
tEXTIpw
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 26. 3. Guaranteed by design, not tested in production.
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Figure 26. I/O AC characteristics definition
90% 50% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out T 10% 50% 90% tr(I O)out
Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF
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5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 33). Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 36.
Symbol VIL(NRST)(1) VIH(NRST)
(1)
NRST pin characteristics
Parameter NRST Input low level voltage NRST Input high level voltage NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(2) NRST Input filtered pulse NRST Input not filtered pulse 300 VIN VSS 30 Conditions Min -0.5 2 200 40 50 100 Typ Max 0.8 V VDD+0.5 mV k ns ns Unit
Vhys(NRST) RPU VF(NRST)(1) VNF(NRST)(1)
1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order).
Figure 27. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 36. Otherwise the reset will not be taken into account by the device.
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Electrical characteristics
5.3.14
TIMx characteristics
The parameters given in Table 37 are guaranteed by design. Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 37.
Symbol tres(TIM)
TIMx characteristics
Parameter Timer resolution time Timer external clock frequency on CHx(2) Timer resolution 16-bit counter clock period when the internal clock is selected 1 fTIMxCLK = 24 MHz Conditions(1) Min 1 fTIMxCLK = 24 MHz 41.7 0 fTIMxCLK = 24 MHz 0 fTIMxCLK/2 12 16 65536 2730 65536 x 65536 Max Unit tTIMxCLK ns MHz MHz bit tTIMxCLK s tTIMxCLK s
fEXT ResTIM tCOUNTER
tMAX_COUNT Maximum possible count
fTIMxCLK = 24 MHz
178
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM15, TIM16 and TIM17 timers. 2. CHx is used as a general term to refer to CH1 to CH4 for TIM1, TIM2, TIM3 and TIM4, to the CH1 to CH2 for TIM15, and to CH1 for TIM16 and TIM17.
5.3.15
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 8. The STM32F100xx value line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 38. Refer also to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).
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Electrical characteristics Table 38.
Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
I2C characteristics
Standard mode I2C(1) Fast mode I2C(1)(2) Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 4.7 4.0 250 0
(3)
Unit Max Min 1.3 s 0.6 100 0(4) 1000 300 0.6 s 0.6 0.6 1.3 400 s s pF 900(3) 300 300 ns Max
1. Guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than 4 MHz to achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The maximum hold time of the Start condition only has to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
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Electrical characteristics
Figure 28. I2C bus AC waveforms and measurement circuit(1)

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 39.
SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V)(1)(2)
fSCL (kHz)(3) 400 300 200 100 50 20 I2C_CCR value RP = 4.7 k 0x8011 0x8016 0x8021 0x0064 0x00C8 0x01F4
1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 400 kHz, the tolerance on the achieved speed is of 2%. For other speed ranges, the tolerance on the achieved speed 1%. These variations depend on the accuracy of the external components used to design the application. 3. Guaranteed by design, not tested in production.
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SPI interface characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 8. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) DuCy(SCK) tsu(NSS)(2) th(NSS)(2) tw(SCKH)(2) tw(SCKL)(2) tsu(MI) (2) tsu(SI)(2) th(MI)
(2)
SPI characteristics(1)
Parameter SPI clock frequency Slave mode SPI clock rise and fall time SPI slave input clock duty cycle NSS setup time NSS hold time SCK high and low time Capacitive load: C = 30 pF Slave mode Slave mode Slave mode Master mode, fPCLK = 24 MHz, presc = 4 Master mode Data input setup time Slave mode Master mode Data input hold time Slave mode Data output access time Slave mode, fPCLK = 24 MHz 4 0 2 3tPCLK 10 25 5 15 2 ns 5 5 30 4tPCLK 2tPCLK 50 5 60 12 8 70 ns % Conditions Master mode Min Max 12 MHz Unit
th(SI)(2) ta(SO)
(2)(3)
tdis(SO)(2)(4) Data output disable time Slave mode tv(SO)
(2)(1)
Data output valid time Data output valid time
Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge)
tv(MO)(2)(1) th(SO)(2) th(MO)(2)
Data output hold time
Master mode (after enable edge)
1. Remapped SPI1 characteristics to be determined. 2. Based on characterization, not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Figure 29. SPI timing diagram - slave mode and CPHA = 0
NSS input tc(SCK) tSU(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN th(SI) B I T1 IN
Electrical characteristics
th(NSS)
tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) LSB OUT
tv(SO) MS B O UT
th(SO) BI T6 OUT
tdis(SO)
LSB IN
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Figure 30. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input tSU(NSS)
SCK Input
tc(SCK)
th(NSS)
CPHA=1 CPOL=0 CPHA=1 CPOL=1
tw(SCKH) tw(SCKL) tr(SCK) tf(SCK)
ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN
tv(SO) MS B O UT th(SI)
th(SO) BI T6 OUT
tdis(SO) LSB OUT
B I T1 IN
LSB IN
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Figure 31. SPI timing diagram - master mode(1)
High NSS input tc(SCK)
SCK Input SCK Input
CPHA= 0 CPOL=0 CPHA= 0 CPOL=1
CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO)
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tr(SCK) tf(SCK) BI T6 IN LSB IN
LSB OUT
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
HDMI consumer electronics control (CEC)
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics.
5.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 8.
Note:
It is recommended to perform a calibration after each power-up.
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Table 41.
Symbol VDDA VREF+ IVREF fADC fS(2) fTRIG(2) VAIN(3) RAIN(2) RADC(2) CADC(2) tCAL(2) tlat(2) tlatr(2) tS(2) tSTAB(2) tCONV(2)
Electrical characteristics
ADC characteristics
Parameter Power supply Positive reference voltage Current on the VREF input pin ADC clock frequency Sampling rate External trigger frequency fADC = 12 MHz 0.6 0.05 Conditions Min 2.4 2.4 160(1) Typ Max 3.6 VDDA 220(1) 12 1 823 17 Conversion voltage range External input impedance Sampling switch resistance Internal sample and hold capacitor Calibration time Injection trigger conversion latency Regular trigger conversion latency Sampling time Power-up time Total conversion time (including sampling time) fADC = 12 MHz fADC = 12 MHz 5.9 83 fADC = 12 MHz 0.214 3 fADC = 12 MHz
(4)
Unit V V A MHz MHz kHz 1/fADC V k k pF s 1/fADC s 1/fADC s 1/fADC s 1/fADC s s 1/fADC
0 (VSSA tied to ground) See Equation 1 and Table 42 for details
VREF+ 50 1 8
0.143 2(4) 0.125 17.1 239.5 0 1 21
fADC = 12 MHz
1.5 0 1.17
14 to 252 (tS for sampling +12.5 for successive approximation)
1. Based on characterization results, not tested in production. 2. Guaranteed by design, not tested in production. 3. In devices delivered in LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally connected to VSSA), see Table 4: STM32F100xx pin definitions and Figure 6. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 41.
Equation 1: RAIN max formula: TS R AIN ------------------------------------------------------------- - R ADC N+2 f ADC C ADC ln 2
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The above formula (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 42.
RAIN max for fADC = 12 MHz(1)
Ts (cycles) tS (s) 0.125 0.625 1.125 2.375 3.45 4.625 5.96 20 0.4 5.9 11.4 25.2 37.2 50 NA NA RAIN max (k)
1.5 7.5 13.5 28.5 41.5 55.5 71.5 239.5
1. Guaranteed by design, not tested in production.
Table 43.
Symbol ET EO EG ED EL
ADC accuracy - limited test conditions(1)(2)
Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Test conditions fPCLK2 = 24 MHz, fADC = 12 MHz, RAIN < 10 k, VDDA = 3 V to 3.6 V VREF+ = VDDA TA = 25 C Measurements made after ADC calibration Typ 1.3 1 0.5 0.7 0.8 Max 2.2 1.5 1.5 1 1.5 LSB Unit
1. ADC DC accuracy values are measured after internal calibration. 2. Based on characterization, not tested in production.
Table 44.
Symbol ET EO EG ED EL
ADC accuracy(1) (2) (3)
Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Test conditions fPCLK2 = 24 MHz, fADC = 12 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V TA = Full operating range Measurements made after ADC calibration Typ 2 1.5 1.5 1 1.5 Max 5 2.5 3 2 3 LSB Unit
1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges. 3. Based on characterization, not tested in production.
Note:
ADC accuracy vs. negative injection current: Injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to
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Electrical characteristics
add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. Figure 32. ADC accuracy characteristics
V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096
EG 4095 4094 4093 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1) ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
5
6
7
4093 4094 4095 4096 VDDA
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Figure 33. Typical connection diagram using the ADC
VDD VT 0.6 V AINx VT 0.6 V IL1 A STM32F10xxx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1)
RAIN(1)
VAIN Cparasitic
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1. Refer to Table 41 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 34 or Figure 35, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.
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Figure 34. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F10xxx
V REF+
1 F // 10 nF
V DDA
1 F // 10 nF V SSA/V REF-
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1. VREF+ is available on 100-pin packages and on TFBGA64 packages. VREF- is available on 100-pin packages only.
Figure 35. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F10xxx
VREF+/VDDA
1 F // 10 nF
VREF-/VSSA
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1. VREF+ and VREF- inputs are available only on 100-pin packages.
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Electrical characteristics
5.3.17
Table 45.
Symbol VDDA VREF+ VSSA RLOAD RO(1)
(2)
DAC electrical specifications
DAC characteristics
Parameter Analog supply voltage Reference supply voltage Ground Resistive load with buffer ON Min 2.4 2.4 0 5 Typ Max(1) 3.6 3.6 0 Unit V V V k When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) and (0xEAB) at VREF+ = 2.4 V It gives the maximum output excursion of the DAC. VREF+ must always be below VDDA Comments
Impedance output with buffer OFF
15
k
CLOAD(1)
Capacitive load
50
pF
DAC_OUT Lower DAC_OUT voltage with buffer min(1) ON DAC_OUT Higher DAC_OUT voltage with buffer ON max(1) DAC_OUT Lower DAC_OUT voltage with buffer min(1) OFF DAC_OUT Higher DAC_OUT voltage with buffer max(1) OFF DAC DC current consumption in quiescent mode (Standby mode)
0.2
V
VDDA - V 0.2 0.5 mV VREF+ V - 1LSB
IDDVREF+
220
A
With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, middle code (0x800) on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs Given for the DAC in 10-bit configuration Given for the DAC in 12-bit configuration Given for the DAC in 10-bit configuration Given for the DAC in 12-bit configuration
380 IDDA DAC DC current consumption in quiescent mode (Standby mode) 480
A
A
0.5 DNL(3) Differential non linearity Difference between two consecutive code-1LSB) 2 Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) 1 4
LSB
LSB LSB LSB
INL(3)
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Electrical characteristics Table 45.
Symbol
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
DAC characteristics (continued)
Parameter Min Typ Max(1) 10 Unit mV LSB LSB % Comments Given for the DAC in 12-bit configuration Given for the DAC in 10-bit at VREF+ = 3.6 V Given for the DAC in 12-bit at VREF+ = 3.6 V Given for the DAC in 12bit configuration
Offset(3)
Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2)
3 12
Gain error(3)
Gain error
0.5
Settling time (full scale: for a 10-bit input code transition between the tSETTLING( lowest and the highest input codes 3) when DAC_OUT reaches final value 1LSB Update rate(3) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB)
3
4
s
CLOAD 50 pF, RLOAD 5 k
1
MS/s CLOAD 50 pF, RLOAD 5 k CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. No RLOAD, CLOAD = 50 pF
Wakeup time from off state (Setting tWAKEUP(3) the ENx bit in the DAC Control register) PSRR+ (1) Power supply rejection ratio (to VDDA) (static DC measurement
6.5
10
s
-67
-40
dB
1. Guaranteed by characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Guaranteed by characterization, not tested in production.
Figure 36. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC Buffer(1) R LOAD 12-bit digital to analog converter DACx_OUT
C LOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.
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Electrical characteristics
5.3.18
Table 46.
Symbol TL(1) Avg_Slope V25(1) tSTART(2) TS_temp(3)(2)
(1)
Temperature sensor characteristics
TS characteristics
Parameter VSENSE linearity with temperature Average slope Voltage at 25C Startup time ADC sampling time when reading the temperature 4.0 1.32 4 Min Typ Max Unit C mV/C V s s
1
4.3 1.41
2
4.6 1.50 10 17.1
1. Guaranteed by characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations.
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Package characteristics
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
6
6.1
Package characteristics
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
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Package characteristics
Figure 37. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline(1)
0.25 mm 0.10 inch GAGE PLANE k D D1 D3
75 76 51
Figure 38. Recommended footprint(1)(2)
75
51
L L1 C
76
0.5
50
0.3
50
16.7
14.3
b E3 E1 E
100
26 1.2
1
100 26 25
25 12.3
Pin 1 1 identification e
ccc
C
16.7
A1 A2 A SEATING PLANE C
1L_ME
ai14906
1. Drawing is not to scale. 2. Dimensions are in millimeters.
Table 47.
Symbol
LQPF100 - 14 x 14 mm, 100-pin low-profile quad flat package mechanical data
millimeters Min Typ Max 1.60 0.05 1.35 0.17 0.09 15.80 13.80 16.00 14.00 12.00 15.80 13.80 16.00 14.00 12.00 0.50 0.45 0.60 1.00 0 3.5 0.08 7 0.0 0.75 0.0177 16.2 14.2 0.622 0.5433 1.40 0.22 0.15 1.45 0.27 0.2 16.2 14.2 0.002 0.0531 0.0067 0.0035 0.622 0.5433 0.6299 0.5512 0.4724 0.6299 0.5512 0.4724 0.0197 0.0236 0.0394 3.5 0.0031 7.0 0.0295 0.6378 0.5591 0.0551 0.0087 Min inches(1) Typ Max 0.063 0.0059 0.0571 0.0106 0.0079 0.6378 0.5591
A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Figure 39. LQFP64 - 10 x 10 mm, 64 pin low-profile quad flat package outline(1)
D D1 D3 48 49 b L1 E3 E1 E 33 32 ccc C A A2
Figure 40. Recommended footprint(1)(2)
48 33 0.3 49 0.5 32
12.7
10.3
10.3 64 17 1.2
K
A1 64 17 Pin 1 identification 1 16
L
1 7.8
16
c
12.7
5W_ME
ai14909
1. Drawing is not to scale. 2. Dimensions are in millimeters.
Table 48.
Symbol
LQFP64 - 10 x 10 mm, 64-pin low-profile quad flat package mechanical data
millimeters Min Typ Max 1.60 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 Number of pins 7 0.75 0 0.0177 1.40 0.22 0.15 1.45 0.27 0.20 0.0020 0.0531 0.0067 0.0035 0.4724 0.3937 0.4724 0.3937 0.0197 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079
A A1 A2 b c D D1 E E1 e L L1
N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
Figure 41. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline
B A A1 e D D1 A F
H G F E E1 D C B A e 1 A3 A4 A2 Seating C plane Bottom view
ME_R8
F
E
2
3
4
5
6
7
8
A1 ball pad corner
Ob (64 balls)
1. Drawing is not to scale.
Table 49.
TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data
millimeters inches(1) Max 1.200 0.150 0.785 0.200 0.600 0.250 4.850 0.300 5.000 3.500 4.850 5.000 3.500 0.500 0.750 0.080 0.150 0.050 5.150 0.1909 0.350 5.150 0.0098 0.1909 0.0118 0.1969 0.1378 0.1969 0.1378 0.0197 0.0295 0.0031 0.0059 0.0020 0.2028 0.0059 0.0309 0.0079 0.0236 0.0138 0.2028 Min Typ Max 0.0472
Symbol Min A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff Typ
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Figure 42. Recommended PCB design rules for pads (0.5 mm pitch BGA)
Pitch D pad Dsm
0.5 mm 0.27 mm 0.35 mm typ (depends on the soldermask registration tolerance) 0.27 mm aperture diameter
Solder paste Dpad Dsm
ai15495
1. Non solder mask defined (NSMD) pads are recommended 2. 4 to 6 mils solder paste screen printing process
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Package characteristics
Figure 43. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline(1)
Seating plane C
Figure 44. Recommended footprint(1)(2)
A A2 A1 ccc b C D D1 k D3 36 25 L1
7.30
c 0.25 mm Gage plane
36 37
0.50 1.20
25 24
0.30
A1
L
9.70
5.80
7.30
0.20
37
24
48 1
13 12
1.20
E3 E1
5.80
E
9.70 ai14911b
48 Pin 1 identification 1 12
13
5B_ME
1. Drawing is not to scale. 2. Dimensions are in millimeters.
Table 50.
Symbol
LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
millimeters Min Typ Max 1.600 0.050 1.350 0.170 0.090 8.800 6.800 9.000 7.000 5.500 8.800 6.800 9.000 7.000 5.500 0.500 0.450 0.600 1.000 0 3.5 0.080 7 0 0.750 0.0177 9.200 7.200 0.3465 0.2677 1.400 0.220 0.150 1.450 0.270 0.200 9.200 7.200 0.0020 0.0531 0.0067 0.0035 0.3465 0.2677 0.3543 0.2756 0.2165 0.3543 0.2756 0.2165 0.0197 0.0236 0.0394 3.5 0.0031 7 0.0295 0.3622 0.2835 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079 0.3622 0.2835
A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
6.2
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in Table 8: General operating conditions on page 34. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where:

TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH),
PI/O max represents the maximum power dissipation on output pins where: taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 51.
Symbol
Package thermal characteristics
Parameter Thermal resistance junction-ambient LQFP 100 - 14 x 14 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP 64 - 10 x 10 mm / 0.5 mm pitch Thermal resistance junction-ambient TFBGA64 - 5 x 5 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP 48 - 7 x 7 mm / 0.5 mm pitch Value 46 45 C/W 65 55 Unit
JA
6.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.
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Package characteristics
6.2.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 52: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F10xxx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application.
Example: high-performance application
Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA x 3.5 V= 175 mW PIOmax = 20 x 8 mA x 0.4 V + 8 x 20 mA x 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 51 TJmax is calculated as follows: - For LQFP64, 45 C/W TJmax = 82 C + (45 C/W x 447 mW) = 82 C + 20.1 C = 102.1 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 52: Ordering information scheme).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA x 3.5 V= 70 mW PIOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW
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Package characteristics
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Using the values obtained in Table 51 TJmax is calculated as follows: - For LQFP100, 46 C/W TJmax = 115 C + (46 C/W x 134 mW) = 115 C + 6.2 C = 121.2 C This is within the range of the suffix 7 version parts (-40 < TJ < 125 C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 52: Ordering information scheme). Figure 45. LQFP100 PD max vs. TA
700 600
PD (mW)
500 400 300 200 100 0 65 75 85 95 105 115 125 135 Suffix 6 Suffix 7
TA (C)
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
Ordering information scheme
7
Ordering information scheme
Table 52.
Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = General-purpose Device subfamily 100 = value line Pin count C = 48 pins R = 64 pins V = 100 pins Flash memory size 4 = 16 Kbytes of Flash memory 6 = 32 Kbytes of Flash memory 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory Package T = LQFP H = BGA Temperature range 6 = Industrial temperature range, -40 to 85 C 7 = Industrial temperature range, -40 to 105 C Internal code B Options xxx = programmed parts TR = tape and real
Ordering information scheme
STM32 F 100 C 6 T 6 B xxx
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.
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Revision history
STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB
8
Revision history
Table 53.
Date 12-Oct-2009
Document revision history
Revision 1 Initial release. TFBGA64 package added (see Table 49 and Table 41). Note 5 modified in Table 4: STM32F100xx pin definitions. IINJ(PIN) modified in Table 6: Current characteristics. Conditions removed from Table 25: Low-power mode wakeup timings. Notes modified in Table 33: I/O static characteristics. Figure 27: Recommended NRST pin protection modified. Note modified in Table 38: I2C characteristics. Figure 28: I2C bus AC waveforms and measurement circuit(1) modified. Table 45: DAC characteristics modified. Figure 36: 12-bit buffered /non-buffered DAC added. TIM2, TIM3, TIM4 and TIM15, TIM16 and TIM17 updated. HDMI-CEC electrical characteristics added. Values added to: - Table 12: Maximum current consumption in Run mode, code with data processing running from Flash - Table 13: Maximum current consumption in Run mode, code with data processing running from RAM - Table 14: STM32F100xxB maximum current consumption in Sleep mode, code running from Flash or RAM - Table 15: Typical and maximum current consumptions in Stop and Standby modes - Table 18: Peripheral current consumption - Table 29: EMS characteristics - Table 30: EMI characteristics - Table 46: TS characteristics Section 5.3.12: I/O port characteristics modified. Added figures: - Figure 12: Maximum current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled - Figure 13: Maximum current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled - Figure 15: Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V - Figure 16: Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V - Figure 17: Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V Changes
26-Feb-2010
2
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STM32F100X4, STM32F100x6, STM32F100x8, STM32F100xB Table 53.
Date
Revision history
Document revision history (continued)
Revision Changes Revision history corrected. Updated Table 6: Current characteristics Values and note updated in Table 16: Typical current consumption in Run mode, code with data processing running from Flash and Table 17: Typical current consumption in Sleep mode, code running from Flash or RAM. Updated Table 15: Typical and maximum current consumptions in Stop and Standby modes Added Figure 14: Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values Typical consumption for ADC1 corrected in Table 18: Peripheral current consumption. Maximum current consumption and Typical current consumption: frequency conditions corrected. Output driving current corrected. Updated Table 30: EMI characteristics fADC max corrected in Table 41: ADC characteristics. Small text changes. Updated Table 31: ESD absolute maximum ratings on page 54 and Table 32: Electrical sensitivities on page 54 Updated Table 43: ADC accuracy - limited test conditions on page 68 and Table 44: ADC accuracy on page 68 Updated Table 24: LSI oscillator characteristics on page 50 Updated Table 43: ADC accuracy - limited test conditions on page 68 and Table 44: ADC accuracy on page 68
30-Mar-2010
3
06-May-2010
4
12-Jul-2010
5
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